Effectiveness of Strain Solutions for Next-Generation MOSFETs

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. The conventional planar bulk MOSFET is difficult to scale down to sub-20nm gate length, due to the worsening performance variability and short channel effects. Thin body transistors, including Multiple-Gate (FinFET & Tri-Gate FET) and Fully Depleted SOI (FD-SOI) MOSFETs are anticipated to replace the current transistor architecture, and will be used in future CMOS technology nodes. Strained Silicon technology is widely used today to boost planar bulk transistor performance. Thus it's technically important to examine the strain-induced performance enhancement in these thin body transistors, for nanometer scale channel length. A comprehensive study on impact of channel stress on ultra-thin-body FD-SOI MOSFETs is presented. It's found that strain-induced mobility enhancement diminishes with Silicon body thickness scaling below 5nm for electrons, but not for holes. Strain-induced carrier transport enhancement is maintained with gate-length scaling. By applying forward back biasing (FBB) through the ultra-thin Buried Oxide layer, both carrier mobilities and their responses to strain get enhanced. For Multiple-gate FETs, the impact of performance enhancement through various types of stressors (including CESL, SiGe Source/Drain, Strained SOI and Metal Gate Last process) is studied, for different fin crystalline orientations and aspect ratios, to provide guidance for 3-D transistor design optimization. i To my parents for their unbounded love and support.